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In recent years, low power design has become one of the prime focuses for digital VLSI circuits. As technology scales down, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book is based on pre-layout and post-layout simulations of a modified 9T full adder and 9T full adder circuit in subthreshold as well as super threshold region. The 9T circuit consists of a new logic, which is used...