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wyszukanych pozycji: 6
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Design Automation for Timing-Driven Layout Synthesis
ISBN: 9781461363934 / Angielski / Miękka / 2012 / 269 str. Termin realizacji zamówienia: ok. 22 dni roboczych (Bez gwarancji dostawy przed świętami) Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be- gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design- ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of...
Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of ...
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cena:
605,23 zł |
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Physical Design for Multichip Modules
ISBN: 9781461361534 / Angielski / Miękka / 2012 / 197 str. Termin realizacji zamówienia: ok. 22 dni roboczych (Bez gwarancji dostawy przed świętami) Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modeling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various...
Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in th...
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cena:
605,23 zł |
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Modeling of Electrical Overstress in Integrated Circuits
ISBN: 9780792395058 / Angielski / Twarda / 1994 / 148 str. Termin realizacji zamówienia: ok. 22 dni roboczych (Bez gwarancji dostawy przed świętami) Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the... Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability co...
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cena:
605,23 zł |
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Physical Design for Multichip Modules
ISBN: 9780792394501 / Angielski / Twarda / 1994 / 197 str. Termin realizacji zamówienia: ok. 22 dni roboczych (Bez gwarancji dostawy przed świętami) Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modeling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various...
Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in th...
|
cena:
605,23 zł |
 |
Design Automation for Timing-Driven Layout Synthesis
ISBN: 9780792392811 / Angielski / Twarda / 1992 / 269 str. Termin realizacji zamówienia: ok. 22 dni roboczych (Bez gwarancji dostawy przed świętami) Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be- gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design- ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of...
Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of ...
|
cena:
605,23 zł |
 |
Modeling of Electrical Overstress in Integrated Circuits
ISBN: 9781461362050 / Angielski / Miękka / 2012 / 148 str. Termin realizacji zamówienia: ok. 22 dni roboczych (Bez gwarancji dostawy przed świętami) Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the... Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability co...
|
cena:
605,23 zł |
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