The Gm/Id Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits: The Semi-Empirical and Compact Model Approaches

ISBN-13: 9781461425052 / Angielski / Miękka / 2012 / 171 str.

Paul Jespers

Opis

In "The g_m/I_D Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits," we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.

Spis treści

Preface. Notations.

1. Sizing the Intrinsic Gain Stage. 1.1 The intrinsic Gain Stage. 1.2 The I.G.S frequency response. 1.3 Sizing the I.G.S. 1.4 The g_m/I_D sizing methodology. 1.5 Conclusions.

2. The Charge Sheet Model revisited. 2.1 Why the Charge Sheet Model? 2.2 The generic drain current equation. 2.3 The C.S.M drain current equation. 2.4 Common source characteristics. 2.5 Weak inversion approximation. 2.6 The g_m/I_D ratio in the common source configuration. 2.7 Common gate characteristic of the Saturated Transistor. 2.8 A few concluding remarks concerning the C.S.M.

3. Graphical interpretation of the Charge Sheet Model. 3.1 A graphical representation of I_D. 3.2 More on the V_T curve. 3.3 Two approximate representations of V_T. 3.4 A few examples illustrating the use of the graphical construction. 3.5 A closer look to the pinch-off region. 3.6 Conclusions.

4. Compact modeling. 4.1 The basic compact model. 4.2 The E.K.V model. 4.3 The common source characteristics I_D(V_G). 4.4 Strong and weak inversion asymptotic approximations derived from the compact model. 4.5 Checking the compact model against the C.S.M. 4.6 Evaluation of g_m/I_D. 4.7 Sizing the Intrinsic Gain Stage by means of the E.K.V. model. 4.8 The common gate g_ms/I_D ratio. 4.9 An earlier compact model. 4.10 Modelling mobility degradation. 4.11 Conclusions.

5. The real transistor. 5.1 Short channel effects. 5.2 Checking the assumption by means of ‘experimental’ evidence. 5.3 Compact model parameters versus bias and gate length. 5.4 Reconstructing I_D(V_DS) characteristics. 5.5 Evaluation of g_x/I_D ratios. 5.6 Conclusions.

6. The real Intrinsic Gain Stage. 6.1 The dependence on bias conditions of the g_m/I_D and g_d/I_D ratios. 6.2 Sizing the I.G.S with semi-empirical data. 6.3 Model driven sizing of the I.G.S. 6.4 Slew-rate considerations. 6.5 Conclusions.

7. The common gate configuration. 7.1 Drain current versus source-to-substrate voltage. 7.2 The cascoded Intrinsic Gain Stage.

8. Sizing the Miller Op. Amp. 8.1 Introductary considerations. 8.2 The Miller Op. Amp. 8.3 Sizing the Miller Operational Amplifier. 8.4 Conclusion.

Annex 1. How to utilize the C.D. ROM data.

Annex 2. The MATLAB toolbox.

Annex 3. Temperature and Mismatch, from C.S.M. to E.K.V.

Annex 4. E.K.V. intrinsic capacitance models.

Bibliography. Index.

Blurb

How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The g_m/I_D methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The g_m/I_D Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.