The Car License Plate Recognition (CLPR) system is one of the important factors in the intelligent traffic engineering field. There are many researches on this topic whether handwritten character recognition, typewritten character recognition or other pattern recognition. CLPR is developed to recognise the car license plate with the implementation of Digital Image Processing (DIP) and Template Matching Algorithm (TMA) approach by using the MATLAB software. This project works on the offline input images collected by using digital camera. The method of this project is based on template matching...
The Car License Plate Recognition (CLPR) system is one of the important factors in the intelligent traffic engineering field. There are many researche...
The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size,...
The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. ...
This book presents the power optimization consumption for Network-on-Chip (NoC) architecture based on network partitioning (NP). The new methodology is proposed to reduce the total power consumption in NoC by utilizing network partitioning (NP) technique to solve the NoC's problem so that it gives a satisfactory performance with the use of high speed, complex ICs in mobile and portable applications. The development of NoC communication power is to estimate the total power consumption in NoC-based communication system. This algorithm will consists of vertex mapping to Processing Elements (PE),...
This book presents the power optimization consumption for Network-on-Chip (NoC) architecture based on network partitioning (NP). The new methodology i...
Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topology of NoC. Analysis performances of VOPD is based on the value of hops involved, since VOPD is divided into bisection and quadsection form....
Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-o...