Delay Aware Topology Generation for Network on Chip

ISBN-13: 9783659693021 / Angielski / Miękka / 2015 / 72 str.

Lit Asrani;Mahyan Fariza

Opis

Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topology of NoC. Analysis performances of VOPD is based on the value of hops involved, since VOPD is divided into bisection and quadsection form. Overall, the report proved that the decreased number of hops of VOPD will give a low rate of delay in NoC performances.

O autorze

Asrani Lit is with Department of Electrical & Electronic, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS). He obtained his master degree of engineering in Electrical (Microelectronics & Computer System) in 2011.