This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic...

This book surveys modeling and implementation of high performance current-steering D/A-converters for digital transceivers in nanometer CMOS technology. Covers performance limitations and offers four current-steering DAC designs in standard 130 nm CMOS.