High-Performance D/A-Converters: Application to Digital Transceivers

ISBN-13: 9783642432750 / Angielski / Miękka / 2015 / 286 str.

Martin Clara

Opis

This book surveys modeling and implementation of high performance current-steering D/A-converters for digital transceivers in nanometer CMOS technology. Covers performance limitations and offers four current-steering DAC designs in standard 130 nm CMOS.

Spis treści

Performance Figures of D/A-Converters.- Static Linearity.- Dynamic Linearity.- Noise-shaped D/A-Converters.- Advanced Current Calibration.

O autorze

Martin Clara received the M.Sc. degree in electrical engineering from Vienna University of Technology, Austria, in 1996 and the Ph.D. degree in electronics from Graz University of Technology, Austria, in 2009.

In 1997 he joined Siemens Microelectronics’ Design Center in Villach, Austria, as an Analog Design Engineer, mainly working on BiCMOS and CMOS linear circuits.

From 2000 to 2009 he was with Infineon Technologies’ Design Center in Villach,Austria, where he designed data converters, linear circuits and RF building blocks in deep-submicron and nanometer CMOS technologies.

Since 2009 he is senior engineer for analog/mixed-signal and RF-design at LANTIQ’s design center, based in Villach, Austria.

His main interests include the implementation of low-voltage and high dynamic range analog front-ends in advanced CMOS technologies, the concept and design of highperformance data converters, as well as RF-CMOS design.

Blurb

This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested.  With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.