Over the past decade, reducing the dynamic switching power was the main focus in many of the proposed low-power circuit techniques. At that time, the off-state leakage power was negligible compared to dynamic power. However, as technology scales into the deep-submicron regime, the increase in leakage power can no longer be neglected. Soon, the biggest challenge that SoC designers must resolve is the fact that transistors for digital and memory circuits will be more and more leaky as technology generations advance. The semiconductor industry must therefore reduce leakage current in chip...

Low-Power Digital VLSI Design: Circuits and Systems addresses both process technologies and device modeling. Power dissipation in CMOS circuits, several practical circuit examples, and low-power techniques are discussed. Low-voltage issues for digital CMOS and BiCMOS circuits are emphasized. The book also provides an extensive study of advanced CMOS subsystem design. A low-power design methodology is presented with various power minimization techniques at the circuit, logic, architecture and algorithm levels.
Features:

• Low-voltage CMOS device modeling, technology...

This excellent survey of state-of-the-art techniques discusses the MTCMOS technology that has emerged as an increasingly popular technique to control the escalating leakage power, while maintaining high performance. It addresses the leakage problem in a number of designs for combinational, sequential, dynamic and current-steering logic.