Wyniki wyszukiwania:
wyszukanych pozycji: 9
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Hardware Acceleration of Eda Algorithms: Custom Ics, FPGAs and Gpus
ISBN: 9781489983336 / Angielski / Miękka / 2014 / 192 str. Termin realizacji zamówienia: ok. 20 dni roboczych. Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications...
Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very l...
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cena:
500,92 zł |
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Hardware Acceleration of Eda Algorithms: Custom Ics, FPGAs and Gpus
ISBN: 9781441909435 / Angielski / Twarda / 2010 / 216 str. Termin realizacji zamówienia: ok. 20 dni roboczych. Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications...
Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very l...
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cena:
382,84 zł |
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Advanced Techniques in Logic Synthesis, Optimizations and Applications
ISBN: 9781441975171 / Angielski / Twarda / 2010 / 423 str. Termin realizacji zamówienia: ok. 20 dni roboczych. This book covers advances in logic synthesis and design, including Boolean Matching, Logic Decomposition, Boolean satisfiability, Advanced Synthesis Techniques and Applications of Logic Design. Also covers techniques for optimizing VLSI integrated circuits.
This book covers advances in logic synthesis and design, including Boolean Matching, Logic Decomposition, Boolean satisfiability, Advanced Synthesis T...
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cena:
612,57 zł |
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On and Off-Chip Crosstalk Avoidance in VLSI Design
ISBN: 9781441909466 / Angielski / Twarda / 2010 / 266 str. Termin realizacji zamówienia: ok. 20 dni roboczych. Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk, which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design. This book focuses on crosstalk avoidance with bus encoding, one of the techniques that selectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before... Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is cr... |
cena:
574,29 zł |
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Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
ISBN: 9780792374077 / Angielski / Twarda / 2001 / 112 str. Termin realizacji zamówienia: ok. 20 dni roboczych. This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our...
This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a ...
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cena:
382,84 zł |
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Practical & Real Time IP Routing Table Compression
ISBN: 9783847321521 / Angielski / Miękka / 2012 / 68 str. Termin realizacji zamówienia: ok. 10-14 dni roboczych. In an attempt to slow the exhaustion of the Internet Protocol (IP) address space, Class-less Inter-Domain Routing (CIDR) was adopted. However, the decision to utilize CIDR also increases the size of the routing table, since it allows an arbitrary partitioning of the routing space. A scheme to reduce the size of routing table in the CIDR context is detailed. A well-known and highly e cient heuristic to perform 2-level logic minimization is extended to compress the routing table. IP routing table represented as a set of completely speci ed logic functions can be compressed to about 25% in size,...
In an attempt to slow the exhaustion of the Internet Protocol (IP) address space, Class-less Inter-Domain Routing (CIDR) was adopted. However, the dec...
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cena:
220,72 zł |
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Strategic System Assurance and Business Analytics
ISBN: 9789811536465 / Angielski / Twarda / 2020 / 602 str. Termin realizacji zamówienia: ok. 20 dni roboczych. |
cena:
689,15 zł |
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Strategic System Assurance and Business Analytics
ISBN: 9789811536496 / Angielski / Miękka / 2021 / 602 str. Termin realizacji zamówienia: ok. 20 dni roboczych. |
cena:
689,15 zł |
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Artificial Intelligence and Machine Learning for Edge Computing
ISBN: 9780128240540 / Angielski / Miękka / 2022 Termin realizacji zamówienia: ok. 18-20 dni roboczych. |
cena:
679,50 zł |
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