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The paper describes a new architecture for implementation of 8 X 8 FDCT (Fast Discrete Cosine Transform) using Distributed Arithmetic (DA). This proposed architecture combines both DA based approaches for distributed input vector and constant coefficients. The described Combined Distributed Arithmetic based DCT (CDA-DCT) architecture has been implemented on Virtex II FPGA, and shows fewer adders and saving exceeding 97% achieved.

This book provides a scheme based on genetic algorithm (GA) to solve the complex triangle elimination (CTE) problem of rectangular dualization approach in VLSI floor planning. Rectangular dualization, where each module is realized as a rectangular area, is an important approach in VLSI floor planning. It is known that if the input adjacency graph contains a complex triangle (CT), i.e. a cycle of three edges that is not a face, and then its rectangular dual does not exists. Elimination of CTs therefore becomes essential before constructing a floor plan. There are two versions of the CTE...

This book is discussed with FPGA implementation of the combined processor of Linear Transform, which can be partially reconfigured. It contains the SIMULINK files (*.mdl) which are block design files of various transform systems such as FFT, DCT, Walsh and Hadamard. From the SIMULINK model appropriate languages (VHDL) for the target boards (FPGA) can be generated. The codes generated from SIMULINK for the target boards are usually convoluted, and may not be the most efficient. But, the time it takes to implement complex systems using SIMULINK is considerably shorter than manually coding in...

This book describes a modulator-demodulator circuit which can execute different modulation schemes like- AM, ASK, BPSK, FSK & QPSK. Both the LUT based implementation and complete VHDL based implementations have done by using digital high frequency carriers. In the first step to realize the whole modulation and demodulation schemes using MATLAB Simulink. The format of a VHDL program is built around the concept of BLOCKS which are the basic building units of a VHDL design.