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Regular processor array implementations lack efficiency due to limitations set by data dependences in order to enable regular data flow. Efficient processor arrays implement data flow of all variables and avoid static variables that require intensive data loads from memory introducing idle processor activity. Most of existing design methods and techniques that map algorithms onto processor arrays are based on linear mappings and just transform the algorithm dependence graphs in space-time graphs. Obtained processor arrays do not reach the required efficiency, producing "bubbles" when the...

This book constitutes the refereed proceedings of the Second International Conference, ICT Innovations 2010, held in Ohrid, Macedonia, in September 2010. The 33 revised papers presented together with 5 invited papers were carefully reviewed and selected. The papers address the following topics: internet applications and services, artificial intelligence, bioinformatics, internet, mobile and wireless technologies, multimedia information systems, computer networks, computer security, e-business, cryptography, high-performance-computing, social networks, e-government, as well as GPU computing.