Evolvable Systems: From Biology to Hardware

ISBN-13: 9783540858560 / Angielski / Miękka / 2008 / 466 str.

Hornby, Gregory S.

Opis

In the mid 1990s, researchers began applying Evolutionary Algorithms (EAs) on a kind of computer chip that could dynamically alter the functionality and physicalconnectionsofits circuits. This combinationofEAs withprogrammable electronics (e. g., Field Programmable Gate Arrays (FPGAs) and Field P- grammable Analogue Arrays (FPAAs)) spawned a new ?eld of Evolutionary Computation (EC) called Evolvable Hardware (EH) with its ?rst workshop, - wards Evolvable Hardware, held in Lausanne, Switzerland in October 1995. This workshop was followed by the First International Conference on Evolvable S- tems: From Biology to Hardware (ICES' 96), held inTsukuba, Japanin October 1996. The second ICES was held in Lausanne, September 1998, the third was in Edinburgh, April 2000, the fourth was in Tokyo, October 2001, the ?fth was in Trondheim, March 2003, the sixth was in Sitges, September 2005, and the seventh was in Wuhan, September 2007. Over the years the EH ?eld has expanded beyond the use of EAs on simple electronic devices to encompass many di?erent combinations of EAs and biol- ically inspired algorithms (BIAs) with various physical devices (or simulations of physical devices). Present research in the ?eld of EH can be split into the two related areas of Evolvable HardwareDesign (EHD) and Adaptive Hardware (AH). Evolvable Hardware Design (EHD) is the use of EAs and BIAs for cre- ing physical devices and designs, examples of where EHD has had some success include analogue and digital electronics, antennas, MEMS chips, opticalsystems aswell asquantum circuits.

Spis treści

Evolution of Analog Circuits.- Unconstrained Evolution of Analogue Computational “QR” Circuit with Oscillating Length Representation.- ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis.- Evolution of Digital Circuits.- A Comparison of Evolvable Hardware Architectures for Classification Tasks.- Hardware Acceleration of an Immune Network Inspired Evolutionary Algorithm for Medical Diagnosis.- A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits.- Hardware-Software Codesign and Platforms for Adaptive Systems.- Evolutionary Graph Models with Dynamic Topologies on the Ubichip.- A Hardware-Software Design Framework for Distributed Cellular Computing.- Hardware/Software Co-synthesis of Distributed Embedded Systems Using Genetic Programming.- Self-Adaptive Networked Entities for Building Pervasive Computing Architectures.- Best Paper Award Competition.- Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study.- Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks.- The Segmental-Transmission-Line: Its Design and Prototype Evaluation.- On Evolutionary Synthesis of Linear Transforms in FPGA.- Evolutionary Robotics.- Towards Efficient Evolutionary Design of Autonomous Robots.- Indirect Online Evolution – A Conceptual Framework for Adaptation in Industrial Robotic Systems.- Development.- A Developmental Gene Regulation Network for Constructing Electronic Circuits.- Discovery and Investigation of Inherent Scalability in Developmental Genomes.- Learning General Solutions through Multiple Evaluations during Development.- Real-World Applications.- Evolving MEMS Resonator Designs for Fabrication.- Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.- Evolutionary Networking.- Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation.- Scalability of a Novel Shifting Balance Theory-Based Optimization Algorithm: A Comparative Study on a Cluster-Based Wireless Sensor Network.- Evolutionary Design of Fault Tolerant Collective Communications.- Evolvable Artificial Neural Networks.- A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs.- Bio-inspired Event Coded Configurable Analog Circuit Block.- Dynamics of Firing Patterns in Evolvable Hierarchically Organized Neural Networks.- Transistor-Level Circuit Evolution.- Evolving Variability-Tolerant CMOS Designs.- Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator.- Extended Posters.- Optimised State Assignment for FSMs Using Quantum Inspired Evolutionary Algorithm.- Evolvable Hardware: A Tool for Reverse Engineering of Biological Systems.- Coevolution of Neuro-developmental Programs That Play Checkers.- Hippocampus-Inspired Spiking Neural Network on FPGA.- Fault-Tolerant Memory Design and Partitioning Issues in Embryonics.- The Input Pattern Order Problem: Evolution of Combinatorial and Sequential Circuits in Hardware.- Neural Development on the Ubichip by Means of Dynamic Routing Mechanisms.- Short Posters.- The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems.- Quantum Bio-inspired Vision Model on System-on-a-Chip (SoC).- Evolutionary Meta Compilation: Evolving Programs Using Real World Engineering Tools.- Waveguide Synthesis by Genetic Algorithms with Multiple Crossover.- Parallel Grammatical Evolution for Circuit Optimization.- Self-organization of Bio-inspired Integrated Circuits.- Artificial Creativity in Linguistics Using Evolvable Fuzzy Neural Networks.

Blurb

This book constitutes the refereed proceedings of the 8th International Conference on Evolvable Systems, ICES 2008, held in Prague, Czech Republic, in September 2008.

The 28 revised full papers and 14 revised poster papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on evolution of analog circuits, evolution of digital circuits, hardware-software codesign and platforms for adaptive systems, evolutionary robotics, development, real-world applications, evolutionary networking, evolvable artificial neural networks, and transistor-level circuit evolution.