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Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been...