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Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum...

This book presents best selected papers presented at the 2nd International Conference on Emerging Trends and Technologies on Intelligent Systems (ETTIS 2022) to be held from 22 – 23 March 2022 in online mode at C-DAC, Noida, India. The book includes current research works in the areas of artificial intelligence, big data, cyber-physical systems, and security in industrial/real-world settings. The book illustrates on-going research results, projects, surveying works, and industrial experiences that describe significant advances in all of the related areas.