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Vertical 3D Memory Technologie
ISBN-13: 9781118760512 / Angielski / Twarda / 2014 / 368 str.
Vertical 3D Memory Technologie
ISBN-13: 9781118760512 / Angielski / Twarda / 2014 / 368 str.
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The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate–all–around and junction–less nanowire memories, stacked thin film and double gate memories, terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of Resistance RAM cross–point arrays, and 2.5D/3D stacking of memory and processor chips with through–silicon–via connections now and remote links later. Key features: Presents a review of the status and trends in 3–dimensional vertical memory chip technologies. Extensively reviews advanced vertical memory chip technology and development Explores technology process routes and 3D chip integration in a single reference
The large scale integration and planar scaling of individual system chips is reaching an expensive limit.
Wydanie ilustrowane
“In summary, Betty Prince has produced a piece of work that is timely and will undoubtedly become a classic text for 3D memory technologies.” (3dincites.com, 30 September 2014)
"As the semiconductor memory industry moves to the third dimension a plethora of competing technologies has arisen each claiming to be the logical, lucrative successor to existing two dimensional versions. The very breadth of these new technologies can be confusing even to experienced industry professionals. Dr Prince′s book appears at the right time to remove this confusion by explaining each technology′s structure, function and potential advantages in a way that is accessible to both interested spectators and those working in the industry. It provides a welcome solid foundation to anyone interested in understanding the various technologies vying for success in this migration.”
—Andrew Walker, Schiltron Corporation, USA
“This is a great review on the current state–of–the–art in the highly topical subject of vertical 3D memories. It comprises the challenges and current solutions of 3D memory integration with respective to different memory technologies. It is a highly valuable resource for researchers and engineers in the field of memory technology.”
— Dr. Stephan Menzel, Forschungszentrum Jülich (PGI–7), Germany
— Jim Handy, TheMemoryGuy.com, OBJECTIVE ANALYSIS Semiconductor Market Research, USA
Acknowledgments xv
1 Basic Memory Device Trends Toward the Vertical 1
1.1 Overview of 3D Vertical Memory Book 1
1.2 Moore’s Law and Scaling 2
1.3 Early RAM 3D Memory 3
1.3.1 SRAM as the First 3D Memory 3
1.3.2 An Early 3D Memory—The FinFET SRAM 6
1.3.3 Early Progress in 3D DRAM Trench and Stack Capacitors 6
1.3.4 3D as the Next Step for Embedded RAM 11
1.4 Early Nonvolatile Memories Evolve to 3D 13
1.4.1 NOR Flash Memory—Both Standalone and Embedded 13
1.4.2 The Charge–Trapping EEPROM 14
1.4.3 Thin–Film Transistor Takes Nonvolatile Memory into 3D 15
1.4.4 3D Microcontroller Stacks with Embedded SRAM and EEPROM 17
1.4.5 NAND Flash Memory as an Ideal 3D Memory 17
1.5 3D Cross–Point Arrays with Resistance RAM 20
1.6 STT–MTJ Resistance Switches in 3D 21
1.7 The Role of Emerging Memories in 3D Vertical Memories 22
References 23
2 3D Memory Using Double–Gate, Folded, TFT, and Stacked Crystal Silicon 25
2.1 Introduction 25
2.2 FinFET—Early Vertical Memories 26
2.2.1 Early FD–SOI FinFET Charge–Trapping Flash Memory 26
2.2.2 FinFET Charge–Trapping Memory on Bulk Silicon 28
2.2.3 Doubling Memory Density Using a Paired FinFET Bit–Line Structure 32
2.2.4 Other Folded Gate Memory Structures and Characteristics 34
2.3 Double–Gate and Tri–Gate Flash 37
2.3.1 Vertical Channel Double Floating Gate Flash Memory 37
2.3.2 Early Double– and Tri–Gate FinFET Charge–Trapping Flash Memories 38
2.3.3 Double–Gate Dopant–Segregated Schottky Barrier CT FinFET Flash 39
2.3.4 Independent Double–Gate FinFET CT Flash Memory 42
2.4 Thin–Film Transistor (TFT) Nonvolatile Memory with Polysilicon Channels 43
2.4.1 Independent Double–Gate Memory with TFT and Polysilicon Channels 43
2.4.2 TFT Polysilicon Channel NV Memory Using Silicon Protrusions to Enhance Performance 46
2.4.3 An Improved Polysilicon Channel TFT for Vertical Transistor NAND Flash 46
2.4.4 Polysilicon TFT CT Memory with Vacuum Tunneling and Al2O3 Blocking Oxide 47
2.4.5 Graphene Channel NV Memory with Al2O3–HfOx–Al2O3 Storage Layer 48
2.5 Double–Gate Vertical Channel Flash Memory with Engineered Tunnel Layer 49
2.5.1 Double–Gate Vertical Single–Crystal Silicon Channel with Engineered Tunnel Layer 49
2.5.2 Polysilicon Substrate TFT CT NAND with Engineered Tunnel Layer 51
2.5.3 Polysilicon Channel Double–Layer Stacked TFT NAND Bandgap–Engineered Flash 52
2.5.4 Eight–Layer 3D Vertical DG TFT NAND Flash with Junctionless Buried Channel 54
2.5.5 Variability in Polysilicon TFT for 3D Vertical Gate NAND Flash 55
2.6 Stacked Gated Twin–Bit (SGTB) CT Flash 55
2.7 Crystalline Silicon and Epitaxial Stacked Layers 56
2.7.1 Stacked Crystalline Silicon Layer TFT for Six–Transistor SRAM Cell Technology 57
2.7.2 Stacked Silicon Layer S3 Process for Production SRAM 61
2.7.3 NAND Flash Memory Development Using Double–Stacked S3 Technology 64
2.7.4 4Gb NAND Flash Memory in 45 nm 3D Double–Stacked S3 Technology 66
References 69
3 Gate–All–Around (GAA) Nanowire for Vertical Memory 72
3.1 Overview of GAA Nanowire Memories 72
3.2 Single–Crystal Silicon GAA Nanowire CT Memories 72
3.2.1 Overview of Single–Crystal Silicon GAA CT Memories 72
3.2.2 An Early GAA Nanowire Single–Crystal Silicon CT Memory 73
3.2.3 Vertically Stacked Single–Crystal Silicon Twin Nanowire GAA CT Memories 74
3.2.4 GAA CT NAND Flash String Using One Single–Crystal SiNW 75
3.2.5 Single–Crystal SiNW CT Memory with High–κ Dielectric and Metal Gate 77
3.2.6 Improvement in Transient Vth Shift After Erase in 3D GAA NW SONOS 78
3.2.7 Semianalytical Model of GAA CT Memories 79
3.2.8 Nonvolatile GAA Single–Crystal Silicon Nanowire Memory on Bulk Substrate 79
3.3 Polysilicon GAA Nanowire CT Memories 82
3.3.1 Polysilicon CT Memories with NW Diameter Comparable to Polysilicon Grain Size 82
3.3.2 Various GAA Polysilicon NW Memory Configurations 83
3.3.3 Trapping Layer Enhanced Polysilicon NW SONOS 85
3.4 Junctionless GAA CT Nanowire Memories 88
3.4.1 3D Junctionless Vertical GAA Silicon NW SONOS Memories 88
3.4.2 Junctionless GAA SONOS Silicon Nanowire on Bulk Substrate for 3D NAND Stack 91
3.4.3 Modeling Erase in Cylindrical Junctionless CT Arrays 92
3.4.4 HfO2–Si3N4 Trap Layer in Junctionless Polycrystal GAA Memory Storage 95
3.5 3D Stacked Horizontal Nanowire Single–Crystal Silicon Memory 95
3.5.1 Process for 3D Stacked Horizontal NW Single–Crystal Silicon Memory 96
3.5.2 A Stacked Horizontal NW Single–Crystal Silicon NAND Flash Memory Development 98
3.6 Vertical Single–Crystal GAA CT Nanowire Flash Technology 103
3.6.1 Overview of Vertical Flash Using GAA SONOS Nanowire Technology 103
3.6.2 Vertical Single–Crystal Silicon 3D Flash Using GAA SONOS Nanowire 103
3.6.3 Fabrication of Two Independent GAA FETs on a Vertical SiNW 104
3.6.4 Vertical 3D Silicon Nanowire CT NAND Array 106
3.7 Vertical Channel Polysilicon GAA CT Memory 107
3.7.1 Multiple Vertical GAA Flash Cells Stacked Using Polysilicon NW Channel 107
3.7.2 Vth Shift Characteristics of Vertical GAA SONOS and/or TANOS Nonvolatile Memory 109
3.7.3 GAA Vertical Pipe CT Gate Replacement Technology 111
3.7.4 Bilayer Poly Channel Vertical Flash for 3D SONOS NAND 112
3.7.5 3D Vertical Pipe CT Low–Resistance (CoSi) Word–Line NAND Flash 112
3.7.6 Vertical Channel CT 3D NAND Flash Cell 114
3.7.7 Read Sensing for Thin–Body Vertical NAND 114
3.8 Graphene Channel Nonvolatile Memory with Al2O3–HfOx–Al2O3 Storage Layer 115
3.9 Cost Analysis for 3D GAA NAND Flash Considering Channel Slope 116
References 117
4 Vertical NAND Flash 119
4.1 Overview of 3D Vertical NAND Trends 119
4.1.1 3D Nonvolatile Memory Overview 119
4.1.2 Architectures of Various 3D NAND Flash Arrays 120
4.1.3 Scaling Trends for 2D and 3D NAND Cells 122
4.2 Vertical Channel (Pipe) CT NAND Flash Technology 124
4.2.1 BiCS CT Pipe NAND Flash Technology 124
4.2.2 Pipe–Shaped BiCS (P–BiCS) NAND Flash Technology 128
4.2.3 Vertical CT Vertical Recess Array Transistor (VRAT) Technology 138
4.2.4 Z–VRAT CT Memory Technology 139
4.2.5 Vertical NAND Chains—VSAT with “PIPE” Process 141
4.2.6 Vertical CT PIPE NAND Flash with Damascene Metal Gate TCAT/VNAND 142
4.2.7 3D NAND Flash SB–CAT Stack 145
4.3 3D FG NAND Flash Cell Arrays 146
4.3.1 3D FG NAND with Extended Sidewall Control Gate 146
4.3.2 3D FG NAND with Separated–Sidewall Control Gate 149
4.3.3 3D FG NAND Flash Cell with Dual CGs and Surrounding FG (DC–SF) 152
4.3.4 3D Vertical FG NAND with Sidewall Control Pillar 155
4.3.5 Trap Characterization in 3D Vertical Channel NAND Flash 157
4.3.6 Program Disturb Characteristics of 3D Vertical NAND Flash 158
4.4 3D Stacked NAND Flash with Lateral BL Layers and Vertical Gate 159
4.4.1 Introduction to Horizontal BL and Vertical Gate NAND Flash 159
4.4.2 A 3D Vertical Gate NAND Flash Process and Device Considerations 160
4.4.3 Vertical Gate NAND Flash Integration with Eight Active Layers 163
4.4.4 3D Stacked CT TFT Bandgap–Engineered SONOS NAND Flash Memory 165
4.4.5 Horizontal Channel Vertical Gate 3D NAND Flash with PN Diode Decoding 168
4.4.6 3D Vertical Gate BE–SONOS NAND Program Inhibit with Multiple Island Gate Decoding 169
4.4.7 3D Vertical Gate NAND Flash BL Decoding and Page Operation 171
4.4.8 An Eight–Layer Vertical Gate 3D NAND Architecture with Split–Page BL 173
4.4.9 Various Innovations for 3D Stackable Vertical Gate 176
4.4.10 Variability Considerations in 2D Vertical Gate 3D NAND Flash 180
4.4.11 An Etching Technology for Vertical Multilayers for 3D Vertical Gate NAND Flash 182
4.4.12 Interference, Disturb, and Programming Algorithms for MLC Vertical Gate NAND 183
4.4.13 3D Vertical Gate NAND Flash Program and Read and Fail–Bit Detection 184
4.4.14 3D p–Channel Stackable NAND Flash with Band–to–Band Tunnel Programming 185
4.4.15 A Bit–Alterable 3D NAND Flash with n–Channel and p–Channel NAND 187
References 189
5 3D Cross–Point Array Memory 192
5.1 Overview of Cross–Point Array Memory 192
5.2 A Brief Background of Cross–Point Array Memories 193
5.2.1 Construction of a Basic Cross–Point Array 193
5.2.2 Stacking Multibit Cross–Point Arrays 194
5.2.3 Methods of Stacking Cross–Point Arrays 196
5.2.4 Stacking Cross–Point Layers for High Density 197
5.2.5 An Example of Unipolar ReRAM 198
5.2.6 An Example of a Bipolar ReRAM 199
5.2.7 Basic Cross–Point Array Operation with a Diode Selector 200
5.2.8 Early Test Chip Using a ReRAM Cross–Point Array with Diode Selector 201
5.3 Low–Resistance Interconnects for Cross–Point Arrays 203
5.3.1 Model of Low Resistance Interconnects for Cross–Point Arrays 203
5.3.2 A Cross–Point Array Grid with Low–Resistivity Nanowires 206
5.3.3 A Cross–Point Array Using Two Nickel Core Nanowires 206
5.3.4 Resistive Memory Using Single–Wall Carbon Nanotubes 207
5.4 Cross–Point Array Memories Without Cell Selectors 207
5.4.1 Early Model of Bipolar Resistive Switch in Selectorless Cross–Point Array 208
5.4.2 Sneak Path Leakage in a Selectorless Cross–Point Array 210
5.4.3 Effect of Parasitic Resistance on Maximum Size of a Selectorless Cross–Point Array 212
5.4.4 Effect of Nonlinearity on I–V Characteristics of Selectorless Memory Element 215
5.4.5 Self–Rectifying ReRAM Requirements in Cross–Point Arrays 216
5.4.6 A Cross–Point Array Model for Line Resistance and Nonlinear Devices 217
5.5 Examples of Selectorless Cross–Point Arrays 217
5.5.1 Example of Nonlinearity in a Selectorless Cross–Point Array 217
5.5.2 Example of High–Resistive Memory Element in Selectorless Cross–Point Array 218
5.5.3 Design Techniques for Nonlinear Selectorless Cross–Point Arrays Using ReRAMs 221
5.5.4 Film Thickness and Scaling Effects in Cross–Point Selectorless ReRAM 222
5.5.5 Vertical HfOx ReRAM 3D Cross–Point Array Without Cell Selector 223
5.5.6 Dopant Selection Rules for Tuning HfOx ReRAM Characteristics 224
5.5.7 High–Resistance CB–ReRAM Memory Element to Avoid Sneak Current 225
5.5.8 Electromechanical Diode Cell for a Cross–Point Nonvolatile Memory Array 226
5.6 Unipolar Resistance RAMs with Diode Selectors in Cross–Point Arrays 227
5.6.1 Overview of Unipolar ReRAMS with Diode Selectors in Cross–Point Arrays 227
5.6.2 A Unipolar ReRAM with Silicon Diode for Cross–Point Array 228
5.6.3 CuOx–InZnOx Heterojunction Thin–Film Diode with NiO ReRAM 230
5.6.4 Unipolar NiO ReRAM Ireset and SET–RESET Instability 232
5.6.5 HfOx–AlOy Unipolar ReRAM with Silicon Diode Selector in Cross–Point Array 232
5.6.6 TiN–TaOx–Pt MIM Selector for Pt–TaOx–Pt Unipolar ReRAM Cross–Point Array 234
5.6.7 Self–Rectifying Unipolar Ni–HfOx Schottky Barrier ReRAM 234
5.6.8 Schottky Barriers for Self–Rectifying Unidirectional Cross–Point Array 236
5.6.9 Thermally Induced Set Operation for Unipolar ReRAM with Diode Selector 237
5.7 Unipolar PCM with Two–Terminal Diodes for Cross–Point Array 238
5.7.1 Background of Phase–Change Memory in a Cross–Point Array 238
5.7.2 PCMs in Cross–Point Arrays with Polysilicon Diodes 239
5.7.3 Cross–Point Array with PCM and Carbon Nanotube Electrode 240
5.7.4 Cross–Point Array with MIEC Access Devices and PCM Elements 241
5.7.5 Threshold Switching Access Devices for ReRAM Cross–Point Arrays 243
5.7.6 p–n Diode Selection Devices for PCM 244
5.7.7 Epitaxial Diode Selector for PCM in Cross–Point Arrays 245
5.7.8 Dual–Trench Epitaxial Diode Array for High–Density PCM 245
5.8 Bipolar Resistance RAMS With Selector Devices in Cross–Point Arrays 246
5.8.1 VO2 Select Device for Bipolar ReRAM in Cross–Point Array 246
5.8.2 Threshold Select Devices for Bipolar Memory Elements in Cross–Point Arrays 246
5.8.3 Vertical Bipolar Switching Polysilicon n–p–n Diode for Cross–Point Array 249
5.8.4 Two–Terminal Diode Steering Element for 3D Cross–Point ReRAM Array 250
5.8.5 Varistor–Type Bidirectional Switch for 3D Bipolar ReRAM Array 250
5.8.6 Bidirectional Threshold Vacuum Switch for 3D 4F2 Cross–Point Array 251
5.8.7 Bidirectional Schottky Diode Selector 252
5.8.8 Bipolar ReRAM with Schottky Self–Rectifying Behavior in the LRS 254
5.8.9 Self–Rectifying Bipolar ReRAM Using Schottky Barrier at Ta–TaOx Interface 255
5.8.10 Diode Effect of Pt–In2Ga2ZnO7 Layer in TiO2–type ReRAM 255
5.8.11 Confined NbO2 as a Selector in Bipolar ReRAMs 256
5.9 Complementary Switching Devices and Arrays 256
5.9.1 Complementary Resistive Switching for Dense Crossbar Arrays 256
5.9.2 CRS Memory Using Amorphous Carbon and CNTs 257
5.9.3 Complementary Switching in Metal–Oxide ReRAM for Crossbar Arrays 259
5.9.4 CRSs Using a Heterodevice 260
5.9.5 Self–Selective W–VO2–Pt ReRAM to Reduce Sneak Current in ReRAM Arrays 261
5.9.6 Hybrid Nb2O5–NbO2 ReRAMwith Combined Memory and Selector 263
5.9.7 Analysis of Complementary ReRAM Switching 264
5.9.8 Complementary Stacked Bipolar ReRAM Cross–Point Arrays 266
5.9.9 Complementary Switching Oxide–Based Bipolar ReRAM 266
5.10 Toward Manufacturable ReRAM Cells and Cross–point Arrays 267
5.10.1 28 nm ReRAM and Diode Cross–Point Array in CMOS–Compatible Process 267
5.10.2 Double–Layer 3D Vertical ReRAM for High–Density Arrays 268
5.10.3 Study of Cell Performance for Different Stacked ReRAM Geometries 269
5.11 STT Magnetic Tunnel Junction Resistance Switches in Cross–Point Array Architecture 269
5.11.1 High–Density Cross–Point STT Magnetic Tunnel Junction Architecture 269
References 271
6 3D Stacking of RAM–Processor Chips Using TSV 275
6.1 Overview of 3D Stacking of RAM–Processor Chips with TSV 275
6.2 Architecture and Design of TSV RAM–Processor Chips 280
6.2.1 Overview of Architecture and Design of Vertical TSV Connected Chips 280
6.2.2 Repartitioning For Performance by Increasing the Number of Memory Banks 280
6.2.3 Using a Global Clock Distribution Technique to Improve Performance 282
6.2.4 Stacking eDRAM Cache and Processor for Improved Performance 282
6.2.5 Using Decoupling Scheduling of the Memory Controller to Improve Performance 283
6.2.6 Repartitioning Multicore Processors and Stacked RAM for Improved Performance 283
6.2.7 Increasing Performance and Lowering Power in Low–Power Mobile Systems 287
6.2.8 Increasing Performance of Memory Hierarchies with 3D TSV Integration 287
6.2.9 Adding Storage–Class Memory to the Memory Hierarchy 289
6.2.10 Improving Performance Using 3D Stacked RAM Modeling 290
6.3 Process and Fabrication of Vertical TSV for Memory and Logic 292
6.3.1 Passive TSV Interposers for Stacked Memory–Logic Integration 292
6.3.2 Process Fabrication Methods and Foundries for Early 2.5D and 3D Integration 295
6.3.3 Integration with TSV Using a High–κ–Metal Gate CMOS Process 296
6.3.4 Processor with Deep Trench DRAM TSV Stacks and High–κ–Metal Gate 297
6.4 Process and Fabrication Issues of TSV 3D Stacking Technology 299
6.4.1 Using Copper TSV for 3D Stacking 299
6.4.2 Air Gaps for High–Performance TSV Interconnects for 3D ICs 300
6.5 Fabrication of TSVs 301
6.5.1 Using TSVs at Various Stages in the Process 301
6.5.2 Stacked Chips using Via–Middle Technology 303
6.6 Energy Efficiency Considerations of 3D Stacked Memory–Logic Chip Systems 306
6.6.1 Overview of Energy Efficiency in 3D Stacked Memory–Logic Chip Systems 306
6.6.2 Energy Efficiency for a 3D TSV Integrated DRAM–Controller System 306
6.6.3 Adding an SRAM Row Cache to Stacked 3D DRAM to Minimize Energy 308
6.6.4 Power Delivery Networks in 3D ICs 311
6.6.5 Using Near–Threshold Computing for Power Reduction in a 3D TSV System 312
6.7 Thermal Characterization Analysis and Modeling of RAM–Logic Stacks 314
6.7.1 Thermal Management of Hot Spots in 3D Chips 314
6.7.2 Thermal Management in 3D Chips Using an Interposer with Embedded TSV 314
6.7.3 Thermal Management of TSV DRAM Stacks with Logic 314
6.7.4 Thermal Management of a 3D TSV SRAM on Logic Stack 316
6.8 Testing of 3D Stacked TSV System Chips 316
6.8.1 Using BIST to Reduce Testing for a Logic and DRAM System Stack 316
6.8.2 Efficient BISR and Redundancy Allocation in 3D RAM–Logic Stacks 316
6.8.3 Direct Testing of Early SDRAM Stacks 319
6.9 Reliability Considerations with 3D TSV RAM–Processor Chips 320
6.9.1 Overview of Reliability Issues in 3D TSV Stacked RAM–Processor Chips 320
6.9.2 Variation Issues in Stacked 3D TSV RAM–Processor Chips 320
6.9.3 Switching and Decoupling Noise in a 3D TSV–Based System 321
6.9.4 TSV–Induced Mechanical Stress in CMOS 324
6.10 Reconfiguring Stacked TSV Memory Architectures for Improved Performance 326
6.10.1 Overview of Potential for Reconfigured Stacked Architectures 326
6.10.2 3D TSV–based 3D SRAM for High–Performance Platforms 326
6.10.3 Waveform Capture with 100 GB/s I/O, 4096 TSVs and an Active Si Interposer 329
6.10.4 3D Stacked FPGA and ReRAM Configuration Memory 330
6.10.5 Cache Architecture to Configure Stacked DRAM to Specific Applications 330
6.10.6 Network Platform for Stacked Memory–Processor Architectures 331
6.10.7 Multiplexing Signals to Reduce Number of TSVs in IC Die Stacking 332
6.10.8 3D Hybrid Cache with MRAM and SRAM Stacked on Processor Cores 333
6.10.9 CMOS FPGA and Routing Switches Made with ReRAM Devices 333
6.10.10 Dynamic Configurable SRAM Stacked with Various Logic Chips 333
6.11 Stacking Memories Using Noncontact Connections with Inductive Coupling 333
6.11.1 Overview of Noncontact Inductive Coupling of Stacked Memory 333
6.11.2 Early Concepts of Inductive–Coupling Connections of Stacked Memory Chips 334
6.11.3 Evolution of Inductive–Coupling Connections of NAND Flash Stacks 336
6.11.4 TCI for Replacing Stacking with TSV Connections 338
6.11.5 Processor–SRAM 3D Integration Using Inductive Coupling 339
6.11.6 Optical Interface for Future 3D Stacked Chip Connections 339
References 340
Index 345
Dr Betty Prince has over 30 years’ experience in the semiconductor industry having worked with Texas Instruments, N.V. Philips, Motorola, R.C.A., and Fairchild and is currently CEO of Memory Strategies International. She has authored four books and served from 1991–1994 on the Technical Advisory Board of IEEE Spectrum magazine. She is a Senior Life Member of the IEEE and served as an IEEE SSCS Distinguished Lecturer and on the Program Committee of the IEEE Custom Integrated Circuit conference. She was founder of the JEDEC JC–16 Interface Standards Committee and was active for many years on the JC–42 Memory Committee where she was co–chair of the SRAM standards group. She has been U.S. representative to the IEC SC47A WG3 Memory Standards Committee. Dr Prince has served on the Technical Advisory Board of several memory companies and has been on the Board of Directors of Mosaid Technologies. She holds patents in the memory, processor and interface areas and has degrees in Physics, Math, and Finance with doctoral dissertation in fractal modeling.
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate–all–around and junction–less nanowire memories, stacked thin film and double gate memories, terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of Resistance RAM cross–point arrays, and 2.5D/3D stacking of memory and processor chips with through–silicon–via connections now and remote links later.
Key features:
- Presents a review of the status and trends in 3–dimensional vertical memory chip technologies.
- Extensively reviews advanced vertical memory chip technology and development
- Explores technology process routes and 3D chip integration in a single reference
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