Time-to-Digital Converters

ISBN-13: 9789048186273 / Angielski / Twarda / 2010 / 124 str.

Stephan Henzler

Opis

With ongoing technology scaling high resolution in the voltage domain becomes increasingly troublesome. Time domain resolution, however, is continuously improving as digital circuits become faster in each new technology generation. Time-to-Digital Converters describes the fundamentals of time-to-digital converters (TDC) based on analog and digital conversion principles. An in depth theoretical investigation is provided with respect to quantization, linearity, noise, and variability. Advanced TDC architectures are described that address the challenges of signed time interval measurement, long measurement time, high resolution, high linearity, low-power, variability and calibration, low mismatch among multiple measurements, and suitability for design automation. Resolution enhancement techniques such as pulse-shrinking, Vernier delay-line, local passive interpolation, gated delay-lines, and time amplification are introduced and discussed with respect to operating principle, resolution, power, area, conversion time, susceptibility to variations, and suitability for implementation and mass production. Finally, an overview on TDC applications in phase-locked-loops and analog-to-digital converters is given. Time-to-Digital Converters provides a strong theoretical basis and comprises a unique in depth overview on TDC architectures and conversion principles.

Spis treści

List of Symbols and Abreviations. 1 Foreword. 2 Time-to-Digital Converter Basics. 2.1 Motivation - The Way to the Time Domain. 2.2 Analog Time-to-Digital Converters - The First Generation. 2.3 Fully Digital TDCs - The Second Generation. 2.4 Basic Digital Delay-Line Based TDC. 2.5 Synchronous vs. Asynchronous Time Interval Measurement. 3 Theory of TDC Operation. 3.1 Basic Performance Figures. 3.2 Quantization Error Revisited. 3.3 Non-Linear Imperfections of TDC Characteristic. 3.4 Dynamic Performance and Effective Resolution. 3.5 Timing Figures. 3.6 Noise Shaping in Time-to-Digital Converters. 3.7 Process Variations in TDCs. 4 Advanced TDC Design Issues. 4.1 Bipolar Time-to-Digital Converter. 4.2 Looped Time-to-Digital Converter. 4.3 Linearly Extended TDC Loop. 4.4 Delay-Locked-Loop Based TDC. 4.5 Hierarchical Time-to-Digital Converter. 4.6 Multi-Event Time-to-Digital Converter. 4.7 On-Chip Test and Characterization Engine. 4.8 Time Domain Quantizer. 4.9 Summary TDC Architectures. 5 Time-to-Digital Converters with Sub-Gatedelay Resolution – The Third Generation. 5.1 Sub-Gate Delay Resolution. 5.2 Parallel Scaled Delay Elements. 5.3 Vernier TDC. 5.4 Pulse-Shrinking TDC. 5.5 Local Passive Interpolation TDC. 5.6 Gated Ring Oscillator TDC. 5.7 Time-to-Digital Converter with Time Amplification. 6 Applications for Time-to-Digital Converters. 6.1 Digital Phase Locked Loop. 6.2 TDC based Analog-to-Digital Converter. References. Index.