Parasitic Substrate Coupling in High Voltage Integrated Circuits: Minority and Majority Carriers Propagation in Semiconductor Substrate

ISBN-13: 9783319743813 / Angielski / Twarda / 2018 / 183 str.

Pietro Buccella; Camillo Stefanucci; Maher Kayal

Spis treści

Chapter1: Overview of Parasitic Substrate Coupling.- Chapter2: Design Challenges in High Voltage ICs.- Chapter3: Substrate Modeling with Parasitic Transistors.- Chapter4: TCAD Validation of the Model.- Chapter5: Extraction Tool for the Substrate Network.- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures.- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.

O autorze

Pietro Buccella is a postdoctoral researcher at EPFL in Lausanne, Switzerland. He received the Ph.D. degree in microsystems and microelectronics from EPFL, Switzerland (’16), the M.Sc. degree in electronic engineering from the Polytechnic University of Turin, Italy (’05). From 2005 to 2010, he was an analog IC design engineer at Microchip Technology Switzerland working in the field of sensor interface, high-voltage and power management CMOS integrated circuit design. From 2010 to 2012, he was a security engineer at Kudelski Group, testing the hardware security of microcontroller and smartcard chips. His main research interests include sensor interface, power management and mixed-signal HV IC design.

Camillo Stefanucci is an affiliated research scientist at the École Polytechnique Fédérale de Lausanne (EPFL, Switzerland). He received the Ph.D. degree in Microelectronics from  EPFL, Switzerland (’16),  the M.Sc. degree in electronic engineering from the Polytechnic University of Milan, Italy (’12) and the joined M.Sc. degree in Nanotechnologies from the Polytechnic University of Turin, Italy and the Institut National Polytechnique de Grenoble, France  (’11). He has experience as analog IC designer at the Swiss Center of Microelectronics (CSEM) and ams AG where he develops industrial ASICs. His research and technical interests include latch-up modeling, power management circuits, HV analog design and data converters.

Maher Kayal received M.S. and Ph.D degrees in electrical engineering from the Ecole Polytechnique Fédérale de Lausanne (EPFL, Switzerland) in 1983 and 1989 respectively. He has been with the Electronics laboratories of the Ecole Polytechnique Fédérale de Lausanne (EPFL, Switzerland) since 1990, where he is currently a professor and director of the “Energy Management and Sustainability" section. He has published many scientific papers, coauthor of three text books dedicated to mixed-mode CMOS design and he holds eleven patents. His technical contributions have been in the area of analog and Mixed-signal circuits design including highly linear and tunable sensors microsystems, signal processing and green energy management.

Jean-Michel Sallese is a Senior Scientist at the Ecole Polytechnique Fédérale de Lausanne (Switzerland). His research is oriented towards analytical modeling of multigate semiconductor field effect transistors, modeling minority carrier propagation in semiconductors, simulation of high energy radiation damages in integrated circuits and novel concepts for Ultra High Fluence and Dose Radiation Sensors.

Blurb

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.

The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.

The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.

• Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
• Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
• Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
• Offers design guidelines to reduce couplings by adding specific test protections.