OPTIMAL DG PLACEMENT FOR VOLTAGE IMPROVEMENT USING PSO

ISBN-13: 9786205522585 / Angielski / Miękka / 80 str.

BESTA HARIPRASAD; P. Sujatha; GOTURU SREENIVASAN

Opis

The size and location of DG are the crucial factors in the application of DG for loss minimization. This book presents an algorithm for the identification of bus location using Sensitivity analysis and also an algorithm for the determination of size of the DG using PSO. This methodology is tested on IEEE 15 bus system. By installing DGs at all the potential locations with the determined sizes, the total real power loss of the system has been reduced by 83% and the voltage profile of the system is also improved. The harmonics that are present in the system are reduced by placing capacitors at the optimal locations which are determined by using PSO-HPF algorithm. By placing the capacitors at optimal locations, the voltage profile is also improved.

O autorze

BESTA HARIPRASAD received B.Tech degree in Electrical & Electronics Engineering in 2010 and M.Tech in Electrical Power Engineering in 2013 from J.N.T.U Anathapur. Currently he is pursuing Ph.D in EEE at J.N.T.U. Anathapur .Dr. P Sujatha, Professor in Department of EEE, JNTUA Ananthapur Dr. G Sreenivasan Professor in Department of EEE, PV.K.K.I.