Low-Power High-Resolution Analog to Digital Converters: Design, Test and Calibration

ISBN-13: 9789402405309 / Angielski / Miękka / 2016 / 293 str.

Amir Zjajo; Jose Pineda De Gyvez

Opis

As the demand rises for low-power, low-voltage A/D converters, so do the quality-control issues in these devices, whose nano-level variables are difficult to control. This work looks at improving power efficiency and enhancing testing and debugging techniques.

Spis treści

Forword. Abbrevations. Symbols.

1. Introduction. 1.1. A/D Conversion Systems. 1.2. Remarks on Curent Design and Debugging Practice. 1.3. Motivation. 1.4. Organization.

2. Analog to Digital Conversion. 2.1. High-Speed High-Resolution A/D Converter Architectural Choices. 2.2. Notes on Low Voltage A/D Converter Design. 2.3. A/D Converter Building Blocks. 2.4. A/D Converters: Summary.

3. Design of Multi-Step Analog to Digital Converters. 3.1. Multi-Step A/D Converter Architecture. 3.2. Deisgn Considerations for Non-Ideal Multi-Step A/D Converter. 3.3. Time-Interleaved Front-End Sample-and-Hold Circuit. 3.4. Multi-Step A/D Converter Stage Design. 3.5. Inter-Stage Design and Calibration. 3.6. Experimental Results. 3.7. Conclusion.

4. Multi-Step Analog to Digital Converter Testing. 4.1. Analog ATPG for Quasi-Static Structural Test. 4.2. Design for Testability Concept. 4.3. On-Chip Stimulus Generation for BIST Applications. 4.4. Remarks on Built-In Self-Test Concepts. 4.5. Stochastic Analysis of Deep-Submicron CMOS Process. 4.5. Conclusion.

5. Multi-Step Analog to Digital Converter Debugging. 5.1. Concept of Sensor Networks. 5.2. Estimation of Die-Level Process Variations. 5.3. Debugging of Multi-Step A/D Converter Stages. 5.4. DfT for Full Accessability of Multi-Step Converters. 5.5. Debugging of Time-Interleaved Systems. 5.6. Foreground Calibration. 5.7. Experimental Results. 5.8. Conclusion.

6. Conclusions and Recommendations. 6.1. Summary of Results. 6.3. Recommendations and Future Research.

Appendix. References. Index.

O autorze

Amir Zjajo received the M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000 and PhD degree from Eindhoven University of Technology in 2010, all in the electrical engineering. In 2000, he joined Philips Research Laboratories, Eindhoven, The Netherlands, as a member of the research staff in the Mixed-Signal Circuits and Systems Group. From 2006 until 2009, he was with Corporate Research of NXP Semiconductors as a senior research scientist. In 2009, he joined Delft University of Technology as a Faculty member in the Circuit and Systems Group. Dr. Zjajo has published more then 20 papers in referenced journals and conference proceedings, and holds 2 patents with 7 more pending. He serves as a member of Technical Program Committee of IEEE Design, Automation and Test in Europe Conference, and IEEE International Mixed-Signal Circuits, Sensors and Systems Workshop. His research interests include mixed-signal circuit design, signal integrity and timing and yield optimization of VLSI.

José Pineda de Gyvez received the Ph.d. degree from the Eindhoven University of Technology, The Netherlands, in 1991. From 1991 until 1999 he was a Faculty member in the Department of Electrical Engineering at Texas A&M University, USA. He is currently a Senior Principal at NXP Semiconductors in The Netherlands. Since 2006 he also holds the professorship “Deep Submicron Integration” in the Department of Electrical Engineering at the Eindhoven University of Technology. Dr. Pineda de Gyvez has been Associate Editor in IEEE Transactions on Circuits and Systems Part I and Part II, and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. He is also a member of the editorial board of the Journal of Low Power Electronics. Dr. Pineda has more than 100 combined publications in the fields of testing, nonlinear circuits, and low power design. He is (co)-author of three books, and has a number of granted patents. His work has been acknowledged in academic environments as well as in patent portfolios of many companies. Pineda’s research has been funded by the Dutch Ministry of Science, US Office of Naval Research, US National Science Foundation, among others. Dr. Pineda is an IEEE Fellow.

Blurb

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods.

In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.