Language-Driven Exploration and Implementation of Partially Re-Configurable Asips

ISBN-13: 9781402092961 / Angielski / Twarda / 2008 / 203 str.

Anupam Chattopadhyay; Rainer Leupers

Opis

Increasing complexity of modern embedded systems demands system designers to ramp up their design productivity without compromising performance goals. This is promoted by modern Electronic System Level (ESL) techniques. Language-driven Exploration and Implementation of Partially Re-configurable ASIPs addresses an important segment of the ESL area by modeling partially re-configurable processors via high-level Architecture Description Language (ADL). This approach also hints an imminent evolution in the area of re-configurable system design.

Spis treści

1 Introduction. 2 Background. 2.1 Processor Design: A Retrospection. 2.2 High-level Processor Modelling. 2.3 Library-based Processor Design. 2.4 Partially Re-configurable Processors: A Design Alternative. 2.5 Synopsis. 3 Related Work. 3.1 A Chronological Overview of the Expanding rASIP Design Space. 3.2 rASIP Design: High-level Modelling Approach. 3.3 rASIP Design: Library-based Approach. 3.4 Independent rASIP Design Tools. 3.5 Motivation. 3.6 Synopsis. 4 rASIP Design Space. 4.1 Architecture Design Points. 4.2 Language-based rASIP Modelling. 4.3 Language-based rASIP Design Flow. 4.4 Synopsis. 5 Pre-fabrication Design Space Exploration. 5.1 Pre-fabrication Design Decisions. 5.2 Application Characterization. 5.3 Software Tool-suite Generation for rASIP. 5.4 Partitioning the ISA: Coding Leakage Exploration. 5.5 Synopsis. 6 Pre-fabrication Design Implementation. 6.1 Base Processor Implementation. 6.2 Partitioning the Structure: Specification Aspects. 6.3 Partitioning the Structure: Implementation Aspects. 6.4 Latency: Multiple Clock Domain Implementation. 6.5 Automatic Interface Generation and Storage. 6.6 Background for FPGA Implementation. 6.7 FPGA Implementation: RTL Synthesis. 6.8 Background for Synthesis on FPGA. 6.9 FPGA Synthesis: Mapping and Clustering. 6.10 FPGA Synthesis: Placement and Routing. 6.11 Synopsis. 7 Post-fabrication Design Space Exploration and Implementation. 7.1 Post-fabrication Design Space Exploration. 7.2 Post-fabrication Design Implementation. 7.3 Synopsis. 8 Case Study. 8.1 Introduction. 8.2 Experiments with RISC-based Architecture. 8.3 Experiments with VLIW-based Architecture. 8.4 Experiments with Coarse-grained FPGA Exploration. 8.5 rASIP Modelling for W-CDMA. 9 Past, Present and Future. 9.1 Past. 9.2 Present. 9.3 Future.