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IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection

ISBN-13: 9783319220345 / Angielski / Twarda / 2015 / 154 str.

Khaled Salah Mohamed
IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection Mohamed, Khaled Salah 9783319220345 Springer - książkaWidoczna okładka, to zdjęcie poglądowe, a rzeczywista szata graficzna może różnić się od prezentowanej.

IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection

ISBN-13: 9783319220345 / Angielski / Twarda / 2015 / 154 str.

Khaled Salah Mohamed
cena 201,72 zł
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This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies.Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; Introduce a deep introduction for Verilog for both implementation and verification point of view. Demonstrates how to use IP in applications such as memory controllers and SoC buses.Describes a new verification methodology called bug localization;Presents a novel scan-chain methodology for RTL debugging;Enables readers to employ UVM methodology in straightforward, practical terms."

Kategorie:
Informatyka
Kategorie BISAC:
Technology & Engineering > Electronics - Circuits - General
Computers > Computer Architecture
Computers > Hardware - Mainframes & Minicomputers
Wydawca:
Springer
Seria wydawnicza:
Analog Circuits and Signal Processing
Język:
Angielski
ISBN-13:
9783319220345
Rok wydania:
2015
Wydanie:
2016
Numer serii:
000108233
Ilość stron:
154
Waga:
0.41 kg
Wymiary:
23.39 x 15.6 x 1.12
Oprawa:
Twarda
Wolumenów:
01
Dodatkowe informacje:
Wydanie ilustrowane

1. Introduction.- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection.- 3. Analyzing the Trade-off between Different Memory Cores and Controllers.- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES.- 5. Verilog for Implementation and Verification.- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation.- 7. Conclusions.

Dr. Khaled Salah attended the school of engineering, Department of Electronics and Communications at Ain-Shams University, Egypt, from 1998 to 2003, where he received his B.Sc. degree in Electronics and Communications Engineering with distinction and honor degree. He received his M.Sc. and his Ph.D. degrees in Electronics and Communications in 2008, 2012 respectively. He joined Mentor Graphic Corporation, where he designed many SoC IPs such as AHB, HDMI, HDCP, eMMC, SDcard, HMC. Currently, Dr. Khaled Salah is a Technical Lead at the Emulation division at Mentor Graphic, Egypt. Dr. Khaled Salah has published one book and more than 42 research papers in the top refereed journals and conferences. His research interests are in 3D integration, IP Modeling, and SoC design.

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies.

·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;

·         Introduce a deep introduction for Verilog for both implementation and verification point of view. 

·         Demonstrates how to use IP in applications such as memory controllers and SoC buses.

·         Describes a new verification methodology called bug localization;

·         Presents a novel scan-chain methodology for RTL debugging;

·         Enables readers to employ UVM methodology in straightforward, practical terms.



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