High-Resolution and High-Speed Integrated CMOS Ad Converters for Low-Power Applications

ISBN-13: 9783319872131 / Angielski / Miękka / 2018 / 171 str.

Weitao Li; Fule Li; Zhihua Wang

Spis treści

Introduction.- ADC Architecture.- Reference Voltage Buffer.- Amplification.- Comparator.- Calibration.- Design Case.- Contributions and Future Directions.

O autorze

Weitao Li received the B.S. degree in electronic engineering from Nanjing University of Posts and Telecommunications, Nanjing, China, in 2007, and the M.E. degree in electronic engineering from Tsinghua University, Beijing, China, in 2010. She is now working toward the Ph.D. degree at Institute of Microelectronics of Tsinghua University. Her research interests include analog and mixed-mode integrated circuit design, especially high-performance low-power data converters.

Fule Li received the B.S. and M.S. degrees in electrical engineering from Xidian University, Xi’an, China, in 1996 and 1999, respectively, and the Ph.D. degree in electronic engineering from Tsinghua University, Beijing, China, in 2003. Now he is an Associate Professor in the Institute of Microelectronics of Tsinghua University. His research interests include analog and mixed-mode integrated circuit design, especially high-performance data converters.

Zhihua Wang received t

he B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 1983, 1985, and 1990, respectively. In 1983, he joined the faculty at Tsinghua University, where he has been a full Professor since 1997. From 1992 to 1993, he was a visiting scholar at Carnegie Mellon University. From 1993 to 1994, he was a Visiting Researcher at K. U. Leuven, Belgium. From 2014 to 2015, he was a visiting professor at Hong Kong University of Science and Technology. His current research mainly focuses on CMOS RFIC and biomedical applications, involving RFID, PLL, low-power wireless transceivers, and smart clinic equipment combined with leading edge RFIC and digital image processing techniques. He has co-authored 11 books/chapters, over 160 (439) papers in international journals (conferences), and holds 121 Chinese and 7 US patents.

Professor Wang is an IEEE Fellow, and has served as chairman of IEEE SSCS Beijing Chapter (1999-2009), an AdCom Member of the I

EEE SSCS (2016-2018), a technology program committee member of the IEEE ISSCC (2005-2011), a steering committee member of the IEEE A-SSCC (2004-), the technical program chair for A-SSCC 2013, a guest editor for IEEE JSSC Special Issues (2006.12, 2009.12 and 2014.11), an associate editor of IEEE Trans on CAS-I, II and IEEE Trans on BioCAS, a TPC Member of International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2005-),  IEEE Great Lakes Symposium on VLSI (GLSVLSI) (2007~09, 2011),  IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (2008), and IEEE Int'l Workshop on Radio-Frequency Integration Technology (2007), the general co-chair of IEEE Biomedical Circuits and Systems Conference (BioCAS) (2009 and 2016), the general chair of IEEE Int'l Workshop on Radio-Frequency Integration Technology (2011), the organization committee chair of IEEE Asian Solid-State Circuits Conference (2006 and 2010), and other administrative/expert committee positions in China’s national science and technology projects.

Blurb

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference.

• Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter;
  
• Presents three types of power-efficient architectures of

the high-resolution and high-speed AD converter;

Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.