High Performance Embedded Architectures and Compilers: First International Conference, Hipeac 2005, Barcelona, Spain, November 17-18, 2005, Proceeding

ISBN-13: 9783540303176 / Angielski / Miękka / 2005 / 318 str.

T. Conte; Tom Conte

Opis

Constitutes the refereed proceedings of the First International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2005, held in 2005. The papers are organized in topical sections on analysis and evaluation techniques, novel memory and interconnect architectures, security architecture, and domain specific architectures.

Spis treści

Invited Program.- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications.- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges.- Software Defined Radio – A High Performance Embedded Challenge.- I Analysis and Evaluation Techniques.- A Practical Method for Quickly Evaluating Program Optimizations.- Efficient Sampling Startup for Sampled Processor Simulation.- Enhancing Network Processor Simulation Speed with Statistical Input Sampling.- II Novel Memory and Interconnect Architectures.- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation.- Streaming Sparse Matrix Compression/Decompression.- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs.- III Security Architecture.- Memory-Centric Security Architecture.- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management.- Arc3D: A 3D Obfuscation Architecture.- IV Novel Compiler and Runtime Techniques.- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations.- Induction Variable Analysis with Delayed Abstractions.- Garbage Collection Hints.- V DomainSpecificArchitectures.- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors.- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture.- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems.- A Low-Power DSP-Enhanced 32-Bit EISC Processor.

O autorze

Wen-mei W. Hwu is the Walter J. ("Jerry") Sanders III-Advanced Micro Devices Endowed Chair in Electrical and Computer Engineering in the Coordinated Science Laboratory of the University of Illinois at Urbana-Champaign. From 1997 to 1999, Dr. Hwu served as the chairman of the Computer Engineering Program at the University of Illinois. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.
His research interests are in the areas of architecture, implementation, and software for high-performance computer systems. He is the director of the OpenIMPACT project, which has delivered new compiler and computer architecture technologies to the computer industry since 1987. He also serves as the Soft Systems Theme leader of the MARCO/DARPA Gigascale Silicon Research Center (GSRC) and on the Executive Committees of both the GSRC and the MARCO/DARPA Center for Circuit and System Solutions.
For his contributions to the areas of compiler optimization and computer architecture, he received the 1993 Eta Kappa Nu Outstanding Young Electrical Engineer Award, the 1994 Xerox Award for Faculty Research, the 1994 University Scholar Award of the University of Illinois, the 1997 Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the 1998 ACM SigArch Maurice Wilkes Award, the 1999 ACM Grace Murray Hopper Award, the 2001 Tau Beta Pi Daniel C. Drucker Eminent Faculty Award. He served as the Franklin Woeltge Distinguished Professor of Electrical and Computer Engineering from 2000 to 2004. He is a fellow of IEEE and ACM.