Digital System Verification: A Combined Formal Methods and Simulation Framework

ISBN-13: 9783031798146 / Angielski / Miękka / 2010 / 79 str.

Lun Li;Mitchel Thornton

Opis

Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation. Table of Contents: Introduction / Formal Methods Background / Simulation Approaches / Integrated Design Validation System / Conclusion and Summary

Spis treści

Introduction.- Formal Methods Background.- Simulation Approaches.- Integrated Design Validation System.- Conclusion and Summary.

O autorze

Lun Li received the BS degree from Beijing Jiaotong University, Beijing, in 1997, the MS degree in electrical engineering from University of Tulsa in 2002, and the PhD degree in computer engineering from Southern Methodist University in 2006. He was previously employed as a verification engineer at NVidia and, since 2007, he has been with Texas Instruments, where he is working in formal verification. His interests include formal and semi-formal verification, simulation, computer arithmetic, and EDA.Mitchell A. Thornton received the BSEE degree from Oklahoma State University in 1985, the MSEE degree from the University of Texas, Arlington, in 1990, and the MSCS and PhD degrees from Southern Methodist University in 1993 and 1995, respectively. His industrial experience includes full-time employment at E-Systems (now L-3 Communications) and the Cyrix Corporation where he served in a variety of engineering positions between 1985 and 1992. Since 1995 he has been a faculty member at the University of Arkansas, Mississippi State University, and since 2002, Southern Methodist University where he is currently a professor of computer science and engineering and electrical engineering. His research interests are in the general area of digital circuits and systems design with specific emphasis in EDA/CAD methods including formal verification/validation and simulation of digital systems, multiple-valued logic, and quantum logic and computing. Mitch is currently the chair of the IEEE Computer Society Technical Committee on Multiple-Valued Logic, chair of the IEEE-USA Licensure and Registration Committee, and chair of the NCEES electrical and computer engineering PE examination development committee. He is a senior member of the IEEE, a member of the ACM, and a member of the ASEE.