Quotation ixPreface xiIntroduction xvChapter 1. Basic Definitions 11.1. General points regarding communication 11.2. Main characteristics 31.3. Synchronism and asynchrony 111.4. Coding data 211.5. Communication protocol 221.6. Access arbitration 311.7. Conclusion 45Chapter 2. Transactions and Special Cycles 472.1. Transaction 472.1.1. Transaction pipeline 472.1.2. Splitting the transaction 502.2. Special cycles 512.2.1. Managing interruption 522.2.2. Managing direct memory access 542.2.3. Bus Mastering 552.2.4. Detection and correction of errors 552.2.5. Multiprocessor aspect 552.3. Conclusion 56Chapter 3. Bus Interfaces 573.1. Functional modules 573.2. Associated signals 593.3. Interfacing logic 623.3.1. Transmission lines 633.3.2. Integrity of the signal 643.3.3. Terminating a line 653.3.4. Driver and receiver 673.3.5. Differential and single-ended links 703.3.6. Topologies 723.3.7. Electronic technologies 753.4. Insertion-withdrawal under tension 763.5. Test and debugging 773.6. Bus limits 773.7. Conclusion 81Chapter 4. Bus Classifications 834.1. Multibus architecture 834.1.1. Segmented buses 854.1.2. Hierarchical buses 864.1.3. Multiple buses 874.1.4. Bridge 884.2. Classification of digital system buses 914.2.1. Local bus 914.2.2. Memory buses 934.2.3. Link buses 944.2.4. Expansion slot bus 964.2.5. Expansion buses 1014.2.6. I/O buses 1014.2.7. Backplane and centerplane buses 1024.2.8. Fieldbus 1074.2.9. SoC: from bus to network 1074.2.10. Power bus 1134.3. Summary: bus classifications 119Conclusion of Volume 2 121Exercises 123Acronyms 127References 145Index 155
Philippe Darche : Associate Professor, University of Paris (formerly Paris Descartes / Paris V)