Rashmi Singh (The Pontifical Catholic University of Minas Gerais Brazil), Arun Kumar Chatterjee
In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 m submicron nMOSFET as access...
In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, ...
