For the most recent CMOS technology feature sizes (e.g., 90nm and 65nm and less), leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage power dissipation may come to dominate total power consumption as technology feature sizes shrink. We propose a new method called dual sleep method which reduces leakage current and saves area in a considerable amount. It also saves exact logic state which makes it better than traditional sleep and zigzag techniques. Unlike the stack approach (which saves state), this...
For the most recent CMOS technology feature sizes (e.g., 90nm and 65nm and less), leakage power dissipation has become a major concern. According to...
