Double gate MOSFET is widely used for sub-50nm technology of transistor design .They have immunity to short channel effects, reduced leakage current and high scaling potential. The single gate Silicon-on-insulator (SOI) devices give improved circuit speed and power consumption .But as the transistor size is reduced the close proximity between source and drain reduces the ability of the gate electrode to control the flow of current and potential distribution in the channel. To reduce SCE we need increase gate to channel coupling with respect to source/drain to channel coupling. This book...