As the operating voltage scales down with the technology, SRAM cells have focus at the stability. The 9T SRAM with inherent data stability and capability of reducing the leakage power is adopted to meet the stringent requirements of the low power designs. The circuit techniques used to reduce the power dissipation and delay of these components has been explored optimum power consumption is obtained. The key to data stability is the isolation between the bitlines and the data node in the 9T SRAM cell. The division of read and write sections provide reduction in the leakage power. In order to...