This book contributes the thoroughly refereed post-proceedings of the 4th International Workshop on Power-Aware Computer Systems, PACS 2004, held in Portland, OR, USA in December 2004.
The 12 revised full papers presented were carefully reviewed, selected, and revised for inclusion in the book. The papers span a wide spectrum of topics in power-aware systems; they are organized in topical sections on microarchitecture- and circuit-level techniques, power-aware memory and interconnect systems, and frequency- and voltage-scaling techniques.
This book contributes the thoroughly refereed post-proceedings of the 4th International Workshop on Power-Aware Computer Systems, PACS 2004, held i...
Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the "Memory Wall." To overcome the memory wall, designers have resorted to a hierarchy of cache memory...
Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly ever...
