Alexandre Amory, Marcelo Lubaszewski, Fernando Moraes
Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers...
Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-C...
