The leakage power, power integrity challenges due to spare cells and peak IR drop respectively are addressed in this monograph. The scope of the solution proposed lies in the Physical design level near to design closure where optimization tools have tight resources to fix these challenges. However, there is a lot of scope for future work in other areas of low PM spectrum like at circuit level, architectural level, design level and software coding level. Majority of today's semiconductor designers are not moved to very recent techniques like gate array ECO flows using ECO kits provided by...