NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for...