Static CMOS digital design has robust working performance, where logic levels are kept at the two extremes, either the ground voltage or supply voltage. However, the voltage excursion between the supply voltage and ground at all nodes causes excessive power dissipation. This condition also generates noise over the whole circuitry, which is not desirable especially in mixed signal designs. Current-mode digital design techniques can be a solution for this issue especially whenever the switching activity is high. In the first part, alternative current-mode arithmetic structures are built...
Static CMOS digital design has robust working performance, where logic levels are kept at the two extremes, either the ground voltage or supply voltag...