This book introduced an approach to design and implement an embedded SoPC (System on Programmable Chip) technique with Altera Nios II processor on a FPGA chip for real-time speech recognition system by developing hardware/software with minimum usage of resources (hardware components) and relatively small size software. This reduces the memory utilization, achieved by using Mel Frequency Cepstral Coefficients (MFCCs) technique as feature extraction combined with its first derivative ( MFCCs) including power computation of the speech frames (i.e. E, MFCC, E, and MFCC), called observation vector...