A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is...

A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold...