FPGA-based speed controller for a synchronous machine with an internal current control loop based on a predictive current controller is presented. Due to their complex computation schemes, predictive current controllers implemented in a full digital system are characterized by an inevitable delay in calculating and applying the switching states to the inverter. Consequently, their performances are affected and the achieved sampling frequency is limited. These digital control limitations are mainly due to the processing speed versus computational complexity trade-off. To cope with this...