Latches and flip-flops used in low power sequential circuits are discussed in this book. A synthesis technique for power optimization in combinational logic circuits has been described. A flip flop has been proposed to reduce power consumption in CMOS circuits. A latch has been proposed which is evaluated from the standard ultra voltage latch for low power application. Simulation results show that the proposed latch has the lowest power consumption with no speed penalty. The significant power and area savings can be achieved by using proposed design.