The short-channel and hot-carrier effects that arise when MOSFET devices are scaled down to very short channel lengths is a major topic of research in the area of VLSI technology. Grooved gate MOSFETS alleviate many of these. Here a systematic study of the major electrical characteristics of grooved gate device is done at gate lengths of 100 nm. An optimised process flow is presented to overcome two of its major drawbacks - higher gate-to-source/drain parasitic capacitance and lack of a self-aligned and integrated gate structure. The resulting device exhibits significantly enhanced...