As the feature size of microelectronic devices approaches the deep submicron regime, the process development and integration issues related to gate stack and silicide processing are key challenges. Gate leakage is rising due to direct tunneling. Power and reliability concerns are expected to limit the ultimate scaling of SiO2-based insulators to about 1.5nm. Gate insulators must not deleteriously affect the interface quality, thermal stability, charge trapping, or process integration. Metal gate materials and damascene gates are being investigated, in conjunction with the application of a...