The desire for having a smaller-faster
chip that does more than ever before, has led to shrinking
feature size and growing integration density. This
integration has left designers grappling with increasing
concerns of signal-integrity (SI), timing- closure and
power-consumption. Firstly, the shrinking feature size has
resulted in greater delays. Further, the adjacent wires are
now very close and cause Cross-talk to each others
signals. Traditional designs focus on protecting SI on long
...