Technology scaling has resulted in a
steady increase in transistor speed. However, unlike
transistors, global wires that span across the chip show a
reverse trend of getting slower with shrinking process.
Modern processors are severely constrained by wire delay and
the widening gap between transistors and wires will only
exacerbate the problem. Following the traditional design
approach of adopting a single design point for all global
wires will be suboptimal in terms of both power and
...