Continuous scaling of transistors combined with increased chip area results in the ratio of global wire delay to gate delay increasing at a super-linear rate. Simple RC models have become inadequate for simulation of VLSI circuits. In addition, parasitic inductance and capacitance of IC packages impose limits on the circuit performance at RF frequencies. This book presents modeling of on-chip inductance for chips with ground grids that emulate those used in real circuits. S-parameter characterization of test chips up to 10 GHz shows good agreement with simulation and analytical calculations....
Continuous scaling of transistors combined with increased chip area results in the ratio of global wire delay to gate delay increasing at a su...