Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the designs timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which...