This book investigates the architecture design, physical implementation, result evaluation, and feature analysis of a many-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with respect to each other in a Globally Asynchronous Locally Synchronous fashion. The processor is called Asynchronous Array of simple Processors (AsAP). A 6x6 array has been fabricated in a 0.18 um CMOS technology. The physical design concerns timing...