This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well-known RISC architecture called DLX are analyzed quantitatively. It is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly.
In an appendix all programs to compute the cost and cycle time of the designs described are listed...