Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modeling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various...
Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in th...
Carlos H. Diaz Sung-Mo (Steve) Kang Charvaka Duvvury
Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress inIntegrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the...
Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability co...
Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be- gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design- ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of...
Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of ...
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada- tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in...
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is ...