VLSI CAD has greatly benefited from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of "Boolean Satisfiability" (SAT), e.g. in logic synthesis, verification or design-for-testability. In recent practical applications, BDDs are optimized with respect to new objective functions for design space exploration. The latest trends show a growing number of proposals to fuse the concepts of BDD and SAT.

Advanced BDD Optimization gives a modern presentation of the established as well as of recent concepts. Latest results in BDD optimization...