Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems.
Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to...

Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be- gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design- ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of...

Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to...

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems.
Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to...

Moore's law Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be- gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design- ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of...