Peter Arato Tamas Visegrady Pé Ter Arató
The CAD tool PIPE has been developed in response to the increased speed requirement and complexity of ASIC executable tasks. High level synthesis offers more complex ASIC design solutions, now emerging in academic and industrial design environments. In this timely resource, the applicability of the PIPE tool is considered in the context of the field towards hardware / software co--design and system level synthesis. * Increasing interest in high-level logic synthesis as designs with 200 million transistors on a single chip become commonplace * Step-by-step tutorial in the CAD tool...
The CAD tool PIPE has been developed in response to the increased speed requirement and complexity of ASIC executable tasks. High level synthesis offe...